The continuously increasing complexity of software products requires evermore extensive calculation steps having to be performed in a computer system. This also leads to the necessity of having to process ever increasing volumes of data. For this reason, the semiconductor industry endeavors to develop integrated semiconductor memories, for example DRAM (dynamic random access memory) semiconductor memories which are capable of storing the increasing volume of data. For this reason, the storage capacity of integrated semiconductor memories has been continuously expanded from one memory generation to the next memory generation.
The increased storage capacity hitherto required that the address space of the integrated semiconductor memory also had to be expanded since the memory cells located in the expanded memory zone in comparison with the preceding model of the integrated semiconductor memory have higher addresses. Thus, selecting a memory cell located in this zone of the integrated semiconductor memory requires additional external address connections via which a memory cell in the expanded memory zone is selected.
As long as there are sufficient address connections for driving the integrated semiconductor memory on the main board of a computer, the so-called motherboard, using such an integrated semiconductor memory in a computer does not present problems, as a rule. This generally applies to computers coming from the same generation as the integrated semiconductor memory itself. Similarly, in modern computers, a control circuit, the so called memory controller, will have a sufficient number of driver channels for being able to drive all address connections of the integrated semiconductor memory for accessing memory cells of the integrated semiconductor memory.
However, problems are presented by upgrading a computer of an older generation with integrated semiconductor memories of the new generation if the maximum memory expansion is already installed in such a computer. In general, there are either no longer sufficient connections on a motherboard of such a computer for contacting the integrated semiconductor memory with the expanded memory zone on the mother board or the memory controller of the motherboard is not compatible with the new memory module since it has too few driver channels for driving the integrated semiconductor memory. It is thus not possible to access the expanded memory zone of the integrated semiconductor memory since no further driver channels of the memory controller are available for driving the most significant address connections which are generally required for accessing the expanded memory zone. The computer can no longer be accelerated by means of memory expansion. There is, therefore, a requirement for a memory expansion for a computer so that the integrated semiconductor memory having the greater storage capacity manages with the same number of external address connections as the semiconductor memory having the lesser storage capacity which hitherto existed in the computer.
A further advantage of using memory chips in which it is possible to access the expanded memory zone without also having to drive the most significant address connections lies in the industrial testing of integrated semiconductor memories. The number of driver channels of the test systems used in testing integrated semiconductor memories is limited. Due to this limitation, the parallel testing of integrated semiconductor memories at the end of the production process is restricted. The number of integrated semiconductor memories which can be tested in parallel drops which becomes noticeable negatively in the throughput and, therefore, leads to time losses in the delivery of the parts.
In particular, the testing of the increasing number of memory banks of an integrated semiconductor memory with expanded memory zone has been found to be problematic. Here, too, testing of the additional memory banks is becoming more and more difficult due to the restricted driver resources. The testing of particular addresses, therefore, had to be completely omitted hitherto. The test systems thus only deliver bit fail maps to a restricted extent so that a bank-dependent signature of the analysis is clearly restricted. One possibility of dealing with the problem currently consists in connecting the corresponding address connections in succession by means of jumpers or other additional hardware components. However, using additional hardware represents a very elaborate and complicated solution to the problem.